1. Field of the Invention
The present invention generally relates to a semiconductor device including a transistor with a composite gate structure and a transistor with a single gate structure, and to a method for manufacturing such a semiconductor device. More specifically, the present invention relates to a nonvolatile semiconductor memory device including a nonvolatile memory cell having a composite gate structure of a floating gate and a control gate, and a transistor having a single gate structure of only a control gate, and also a method for manufacturing such a nonvolatile semiconductor memory device.
2. Description of the Related Art
Among nonvolatile semiconductor memory devices in which information stored therein can not be erased even when power sources are turned OFF, the information can be electrically written into the respective memory cells of EPROMs (Electrically Programmable Read-Only Memories), whereas the information can be electrically written into the respective memory cells as well as can be electrically erased from each of these memory cells in EEPROMs (Electrically Erasable Programmable Read-Only Memories).
In general, as a memory cell for such an EPROM and an EEPROM, a MOS transistor with a composite gate structure is employed. The composite gate structure is constituted by stacking a floating gate electrode and a control gate electrode which are made of polycrystalline silicon films with an insulating film interposed therebetween. On the other hand, as a gate electrode of a single gate structure of another MOS transistor other than the memory cell transistor formed in, for example, a peripheral circuit region, two layers of polycrystalline silicon films, which are made simultaneously with forming of the floating gate and the control gate of the memory cell transistor, are utilized so that the steps in manufacturing of the transistor can be simplified. Such a semiconductor memory device structure is disclosed in, for instance, JP-A-59-74677, JP-A-7-183411, and JP-A-548046.
In JP-A-59-74677, the composite gate containing the floating gate and the control gate of the memory transistor, and the single gate structure of the peripheral transistor are both formed by three layers of a first polycrystalline silicon film, an insulating film, and a second polycrystalline silicon film, wherein in the peripheral transistor, the first polycrystalline silicon film is electrically connected via an opening fabricated in the insulating film to the second polycrystalline silicon film in an integral form, so as to provide a structure essentially identical to the gate of the single layer structure. However, the steps in manufacturing the memory device of JP-A-59-74677 would be complicated, since the opening must be formed at a preselected place of the insulating film located between the first polycrystalline silicon film and the second polycrystalline silicon film, which constitute the gate electrode of the peripheral transistor.
In JP-A-7-183411 and JP-A-5-48046, it is disclosed to form the floating gate and the control gate of a memory cell transistor by stacking successively the first polycrystalline silicon film, silicon oxide film and the second polycrystalline silicon film and to form the control gate of the peripheral transistor by stacking the second polycrystalline silicon film directly on the first polycrystalline silicon film. In such a case that the composite gate of the memory cell transistor and the gate electrode of the peripheral transistor are both formed of a lamination of the first and second polycrystalline silicon films, it is required to introduce an impurity such as phosphorous into the first and second polycrystalline silicon films thereby reducing the resistance of the films, since the films are also used as wiring layers. However, any of JP-A-7-183411 and JP-A-5-48046 describes nothing about this matter.
On the other hand, JP-A-2-3289 discloses a composite gate of the memory transistor which is manufactured by successively stacking a first polycrystalline silicon film into which phosphorous is doped at a low concentration, an interlayer insulating film, and a second polycrystalline silicon film into which phosphorous is doped at a high concentration.
Generally speaking, as a method for introducing an impurity such as phosphorous into the first and second polycrystalline silicon films constituting the floating gate and the control gate, there are an ion injection method in which accelerated impurity ions are injected into the polycrystalline silicon films and an vapor phase diffusion method or thermal diffusion method, in which oxyphosphorus chloride is vapored in a furnace, so that phosphorous is diffused from the vapor phase into the polycrystalline silicon films.
However, in the thermal diffusion method, since the impurity concentration is determined by the solid solution degree corresponding to the diffusion temperature, it is difficult to introduce the impurity at a low concentration into the polycrystalline silicon film. When the impurity concentration of the first polycrystalline silicon film of the memory cell transistor is increased, the boundary condition between the gate oxide film and the first polycrystalline silicon film is deteriorated, and the injection or extraction of electrons into or from the first polycrystalline silicon film of the floating gate can not be uniformly carried out, so that the memory cells fail to operate under stable condition.
On the other hand, in the ion injection method, it is difficult due to a breakage of the gate oxide film and/or occurrence of the crystal defects in the substrate to introduce the impurity into the first polycrystalline silicon film by an amount sufficient to lower its resistance. If the resistance of the first polycrystalline silicon film is not sufficiently lowered, then the resistance of the gate electrode made of the first and second polycrystalline silicon films of the peripheral transistor becomes higher. Then, if the resistance of the gate electrode becomes higher, the first polycrystalline silicon film is subjected to depletion state when the voltage is applied to the gate electrode, so that the threshold voltage of the peripheral transistor becomes unstable.
In a conventional nonvolatile semiconductor memory device in which both a memory cell transistor and another transistor other than the memory cell transistor have a two-layer polycrystalline silicon film gate structure, it is difficult to provide the polycrystalline silicon film of the under layer with an impurity concentration which satisfies the necessary condition of the memory cell transistor, as well as the condition required for the another transistor other than the memory cell transistor.
Further, the memory device of JP-A-59-74677 has a problem that since the first and second polycrystalline silicon films constituting the gate electrode disposed at an active region in the region for forming peripheral transistors are connected with each other through the opening formed at a predetermined position in the insulating film interposed therebetween, the impurities, if contained at a high concentration in the second polycrystalline silicon film, may be diffused into the first polycrystalline silicon film through the opening thereby deteriorating the boundary condition between the gate oxide film and the first polycrystalline silicon film.
SUMMARY OF THE INVENTION
An object of the present invention is to provide such a semiconductor device containing a first transistor having a composite gate structure, and a second transistor having a single gate structure. In this semiconductor device, each of the composite gate structure and the single gate structure is fabricated by a lamination of a first polycrystalline silicon film and a second polycrystalline silicon film. Also, an impurity concentration of the first polycrystalline silicon film for constructing the above-described composite gate structure, and an impurity concentration of the first polycrystalline silicon film for constituting the single gate structure can be controlled independently of each other.
According to one aspect of the present invention, a semiconductor device comprises: a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein said first polycrystalline silicon film and said third polycrystalline silicon film have substantially the same thickness; said second polycrystalline silicon film and said fourth polycrystalline silicon film have substantially the same thickness; said first polycrystalline silicon film and said third polycrystalline silicon film have different impurity concentrations controlled independently of each other; and said second polycrystalline silicon film, said fourth polycrystalline silicon film, and said third polycrystalline silicon film have substantially the same impurity concentration.
In a preferred embodiment of the present invention, the impurity concentration of said first polycrystalline silicon film is 1xc3x971018 to 1xc3x971019 atoms/cm3, and the impurity concentration of said third polycrystalline silicon film is 1xc3x971020 to 1xc3x971021 atoms/cm3.
According to another aspect of the present invention, a semiconductor device comprises: a first transistor having a composite gate structure containing a lamination of a first conductive film, an insulating film, and a second conductive film; and a second transistor having a single gate structure containing a third conductive film; wherein said second conductive film and said third conductive film have substantially the same conductivity; said third conductive film has a thickness substantially the same as a total of a thickness of said first conductive film and a thickness of said second conductive film, or a total of a thickness of said first conductive film, a thickness of said insulating film, and a thickness of said second conductive film; and said first conductive film has a conductivity different from any one of a conductivity of said second conductive film and that of said third conductive film.
Furthermore, according to another aspect of the present invention, a semiconductor device comprises: a first transistor having a composite gate structure containing a lamination of a first conductive film, an insulating film formed on said first conductive film, and a second conductive film formed on said insulating film and having a conductivity different from that of said first conductive film; and a second transistor having a single gate structure containing a third conductive film having substantially the same conductivity as that of said second conductive film, and also having substantially the same thickness as a total of a film thickness of said first conductive film and a film thickness of said second conductive film, or a total of a thickness of said first conductive film, a thickness of said insulating film, and a thickness of said second conductive film.
According to one aspect of the present invention, a method for manufacturing a semiconductor device including a first transistor having a composite gate structure and a second transistor having a single gate structure, comprises the steps of: forming a first insulating film on a surface of a first region of a semiconductor substrate and forming a second insulating film on a surface of a second region of the semiconductor substrate; forming a first polycrystalline silicon film over an entire surface of said semiconductor substrate; introducing an impurity at a first predetermined concentration into said first polycrystalline silicon film by ion injection; patterning said first polycrystalline silicon film to a predetermined shape in said first region; forming a third insulating film containing at least a silicon nitride film on at least said first region except for said second region of said semiconductor substrate; forming a second polycrystalline silicon film over an entire surface of said semiconductor substrate; introducing an impurity at a second predetermined concentration higher than said first concentration into said second polycrystalline silicon film by thermal-diffusion; patterning a lamination of said second polycrystalline silicon film, said third insulating film, and said first polycrystalline silicon film into a predetermined pattern in said first region to thereby fabricate said composite gate structure of said first transistor; and patterning a lamination of said first polycrystalline silicon film and said second polycrystalline silicon film into a predetermined pattern in said second region to thereby fabricate said single gate structure of said second transistor.
Moreover, according to another aspect of the present invention, a method for manufacturing a semiconductor device including a first transistor having a composite gate structure and a second transistor having a single gate structure, comprises the steps of: forming a first insulating film on a surface of an active region disposed in a first region of a semiconductor substrate and a second insulating film on a surface of an active region disposed in a second region of the substrate; forming a first conductive film over an entire surface of said semiconductor substrate; introducing an impurity at a first predetermined concentration into said first conductive film by ion-injection; forming a third insulating film above said first conductive film at an area including at least said first region except for said second region, or an area including at least said first region and said active region of said second region except for an element isolation region of said second region; forming a conductive film over the entire surface of said semiconductor substrate; introducing an impurity at a predetermined second concentration higher than said first concentration into said second conductive film by thermal diffusion; patterning a lamination of said second conductive film, said third insulating film, and said first conductive film into a predetermined pattern to thereby fabricate said composite gate structure of said first transistor in the active region of said first region; and patterning a lamination of said first conductive film and said second conductive film into a predetermined pattern to thereby fabricate said single gate structure of said second transistor in the active region of said second region.